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ds97z8x0401 p r e l i m i n a r y 1 1 p reliminary p roduct s pecification z86e04/e08 1 cmos z8 otp m icrocontrollers product devices several key product features of the extensive family of zilog z86e04/e08 cmos otp microcontrollers are presented in the above table. this table enables the user to identify which of the twenty e04/e08 product variants most closely match the user? application requirements. part oscillator operating operating rom number type v cc temperature (kb) package z86e0412pec crystal 4.5v - 5.5v -40 c/105 c 1 18-pin dip z86e0412psc1860 crystal 3.0v - 5.5v 0 c/70 c 1 18-pin dip z86e0412psc1866 crystal 4.5v - 5.5v 0 c/70 c 1 18-pin dip z86e0412psc1903 rc 4.5v - 5.5v 0 c/70 c 1 18-pin dip z86e0412psc1924 rc 3.0v - 5.5v 0 c/70 c 1 18-pin dip z86e0412sec crystal 4.5v - 5.5v -40 c/105 c 1 18-pin soic z86e0412ssc1860 crystal 3.0v - 5.5v 0 c/70 c 1 18-pin soic z86e0412ssc1866 crystal 4.5v - 5.5v 0 c/70 c 1 18-pin soic z86e0412ssc1903 rc 4.5v - 5.5v 0 c/70 c 1 18-pin soic z86e0412ssc1924 rc 3.0v - 5.5v 0 c/70 c 1 18-pin soic z86e0812pec crystal 4.5v - 5.5v -40 c/105 c 2 18-pin dip z86e0812psc1860 crystal 3.0v - 5.5v 0 c/70 c 2 18-pin dip z86e0812psc1866 crystal 4.5v - 5.5v 0 c/70 c 2 18-pin dip z86e0812psc1903 rc 4.5v - 5.5v 0 c/70 c 2 18-pin dip z86e0812psc1924 rc 3.0v - 5.5v 0 c/70 c 2 18-pin dip Z86E0812SEC crystal 4.5v - 5.5v -40 c/105 c 2 18-pin soic z86e0812ssc1860 crystal 3.0v - 5.5v 0 c/70 c 2 18-pin soic z86e0812ssc1866 crystal 4.5v - 5.5v 0 c/70 c 2 18-pin soic z86e0812ssc1903 rc 4.5v - 5.5v 0 c/70 c 2 18-pin soic z86e0812ssc1924 rc 3.0v - 5.5v 0 c/70 c 2 18-pin soic
z86e04/e08 cmos z8 otp microcontrollers zilog 2 p r e l i m i n a r y ds97z8x0401 features n 14 input / output lines n six vectored, prioritized interrupts (3 falling edge, 1 rising edge, 2 timers) n two analog comparators n program options: low noise rom protect auto latch watch-dog timer (wdt) eprom/test mode disable n two programmable 8-bit counter/timers, each with 6-bit programmable prescaler n wdt/ power-on reset (por) n on-chip oscillator that accepts xtal, ceramic resonance, lc, rc, or external clock n clock-free wdt reset n low-power consumption (50 mw typical) n fast instruction pointer (1 m s @ 12 mhz) n ram bytes (125) general description zilog's z86e04/e08 microcontrollers (mcu) are one-time programmable (otp) members of zilog? single-chip z8 mcu family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked rom versions. for applications demanding powerful i/o capabilities, the z86e04/e08's dedicated input and output lines are grouped into three ports, and are configurable under soft- ware control to provide timing, status signals, or parallel i/o. two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and i/o data com- munications. note: all signals with a preceding front slash, ?? are active low, for example: b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: connection circuit device power v cc v dd ground gnd v ss
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 3 1 figure 1. functional block diagram port 3 counter/ timers (2) interrupt control two analog comparators port 2 i/o (bit programmable) flag register pointer general-purpose register file machine timing & inst. control otp program counter vcc gnd xtal port 0 i/o input alu
z86e04/e08 cmos z8 otp microcontrollers zilog 4 p r e l i m i n a r y ds97z8x0401 general description (continued) figure 2. eprom programming mode block diagram address mux eprom rom prot low noise ad 11- 0 z8 mcu z8 port 0 msn port 3 pgm + test mode logic epm p32 /ce xt1 /pgm p30 d7 - 0 ad 11- 0 ad 11- 0 data mux z8 port 2 d7 - 0 /oe p31 vpp p33 d7 - 0
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 5 1 pin description figure 3. 18-pin eprom mode con?uration table 1. 18-pin dip pin identi?ation eprom programming mode pin # symbol function direction 1? d4?7 data 4, 5, 6, 7 in/output 5v cc power supply 6 n/c no connection 7 /ce chip enable input 8 /oe output enable input 9 epm eprom prog mode input 10 v pp prog voltage input 11 clear clear clock input 12 clock address input 13 /pgm prog mode input 14 gnd ground 15?8 d0?3 data 0,1, 2, 3 in/output d4 d5 d6 d7 vcc nc /ce /oe epm d3 d2 d1 d0 gnd /pgm clock clear vpp 18 1 910 figure 4. 18-pin dip/soic mode con?uration table 2. 18-pin dip/soic pin identi?ation standard mode pin # symbol function direction 1? p24?27 port 2, pins 4,5,6,7 in/output 5v cc power supply 6 xtal2 crystal osc. clock output 7 xtal1 crystal osc. clock input 8 p31 port 3, pin 1, an1 input 9 p32 port 3, pin 2, an2 input 10 p33 port 3, pin 3, ref input 11?3 p00?02 port 0, pins 0,1,2 in/output 14 gnd ground 15?8 p20?23 port 2, pins 0,1,2,3 in/output p24 p25 p26 p27 vcc xtal2 xtal1 p31 p32 p23 p22 p21 p20 gnd p02 p01 p00 p33 18 1 910
z86e04/e08 cmos z8 otp microcontrollers zilog 6 p r e l i m i n a r y ds97z8x0401 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only; functional operation of the device at any condition above those indicated in the oper- ational sections of these specifications is not implied. ex- posure to absolute maximum rating conditions for an ex- tended period may affect device reliability. total power dissipation should not exceed 462 mw for the package. power dissipation is calculated as follows: total power dissipation = v dd x [i dd - (sum of i oh )] + sum of [(v dd - v oh ) x i oh ] + sum of (v 0l x i 0l ) parameter min max units note ambient temperature under bias ?0 +105 c storage temperature ?5 +150 c voltage on any pin with respect to v ss ?.7 +12 v 1 voltage on v dd pin with respect to v ss ?.3 +7 v voltage on pins 7, 8, 9, 10 with respect to v ss ?.6 v dd +1 v 2 total power dissipation 1.65 w maximum allowable current out of v ss 300 ma maximum allowable current into v dd 220 ma maximum allowable current into an input pin ?00 +600 m a3 maximum allowable current into an open-drain pin ?00 +600 m a4 maximum allowable output current sinked by any i/o pin 25 ma maximum allowable output current sourced by any i/o pin 25 ma total maximum output current sinked by a port 60 ma total maximum output current sourced by a port 45 ma notes: 1. this applies to all pins except where otherwise noted. maximum current into pin must be 600 m a. 2. there is no input protection diode from pin to v dd (not applicable to eprom mode). 3. this excludes pin 6 and pin 7. 4. device pin is not at an output low state.
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 7 1 standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to ground. positive current flows into the referenced pin (fig- ure 5). capacitance t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. figure 5. test load diagram from output under test 150 pf parameter min max input capacitance 0 10 pf output capacitance 0 20 pf i/o capacitance 0 25 pf
z86e04/e08 cmos z8 otp microcontrollers zilog 8 p r e l i m i n a r y ds97z8x0401 dc electrical characteristics t a = 0 c to +70 c typical note 4 sym parameter v cc [4] min max @ 25 c units conditions notes v inmax max input voltage 3.0v 12 v i in <250 m a 1 5.5v 12 v i in <250 m a 1 v ch clock input high voltage 3.0v 0.8 v cc v cc +0.3 1.7 v driven by external clock generator 5.5v 0.8 v cc v cc +0.3 2.8 v driven by external clock generator v cl clock input low voltage 3.0v v ss ?.3 0.2 v cc 0.8 v driven by external clock generator 5.5v v ss ?.3 0.2 v cc 1.7 v driven by external clock generator v ih input high voltage 3.0v 5.5v 0.7 v cc 0.7 v cc v cc +0.3 v cc +0.3 1.8 2.8 v v v il input low voltage 3.0v 5.5v v ss ?.3 v ss ?.3 0.2 v cc 0.2 v cc 0.8 1.5 v v v oh output high voltage 3.0v v cc ?.4 3.0 v i oh = ?.0 ma 5 5.5v v cc ?.4 4.8 v i oh = ?.0 ma 5 3.0v v cc ?.4 3.0 v low noise @ i oh = ?.5 ma 5.5v v cc ?.4 4.8 v low noise @ i oh = ?.5 ma v ol1 output low voltage 3.0v 0.8 0.2 v i ol = +4.0 ma 5 5.5v 0.4 0.1 v i ol = +4.0 ma 5 3.0v 0.4 0.2 v low noise @ i ol = 1.0 ma 5.5v 0.4 0.1 v low noise @ i ol = 1.0 ma v ol2 output low voltage 3.0v 1.0 1.0 v i ol = +12 ma, 5 5.5v 0.8 0.8 v i ol = +12 ma, 5 v offset comparator input offset voltage 3.0v 25.0 10.0 mv 5.5v 25.0 10.0 mv v lv v cc low voltage auto reset 2.2 3.0 2.8 v @ 6 mhz max. int. clk freq. i il input leakage (input bias current of comparator) 3.0v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc i ol output leakage 3.0v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc v icr comparator input common mode voltage range 0v cc ?.0 v
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 9 1 t a = 0 c to +70 c typical note 4 sym parameter v cc [4] min max @ 25 c units conditions notes i cc supply current 3.0v 3.5 1.5 ma all output and i/o pins floating @ 2 mhz 5,7 5.5v 11.0 6.8 ma all output and i/o pins floating @ 2 mhz 5,7 3.0v 8.0 3.0 ma all output and i/o pins floating @ 8 mhz 5,7 5.5v 15.0 8.2 ma all output and i/o pins floating @ 8 mhz 5,7 3.0v 10.0 3.6 ma all output and i/o pins floating @ 12 mhz 5,7 5.5v 20.0 12.0 ma all output and i/o pins floating @ 12 mhz 5,7 i cc1 standby current 3.0v 2.5 0.7 ma halt mode v in = 0v,v cc @ 2 mhz 5,7 5.5v 4.0 2.5 ma halt mode v in = 0v,v cc @ 2 mhz 5,7 3.0v 4.0 1.0 ma halt mode v in = 0v, v cc @ 8 mhz 5,7 5.5v 5.0 3.0 ma halt mode v in = 0v, v cc @ 8 mhz 5,7 3.0v 4.5 1.5 ma halt mode v in = 0v, v cc @ 12 mhz 5,7 5.5v 7.0 4.0 ma halt mode v in = 0v, v cc @ 12 mhz 5,7 i cc supply current (low noise mode) 3.0v 3.5 1.5 ma all output and i/o pins floating @ 1 mhz 7 5.5v 11.0 6.8 ma all output and i/o pins floating @ 1 mhz 7 3.0v 5.8 2.5 ma all output and i/o pins floating @ 2 mhz 7 5.5v 13.0 7.5 ma all output and i/o pins floating @ 2 mhz 7 3.0v 8.0 3.0 ma all output and i/o pins floating @ 4 mhz 7 5.5v 15.0 8.2 ma all output and i/o pins floating @ 4 mhz 7
z86e04/e08 cmos z8 otp microcontrollers zilog 10 p r e l i m i n a r y ds97z8x0401 dc electrical characteristics (continued) t a = 0 c to +70 c typical note 4 sym parameter v cc [4] min max @ 25 c units conditions notes i cc1 standby current (low noise mode) 3.0v 2.5 0.7 ma halt mode v in = 0v,v cc @ 1 mhz 7 5.5v 4.0 2.5 ma halt mode v in = 0v,v cc @ 1 mhz 7 3.0v 3.0 0.9 ma halt mode v in = 0v,v cc @ 2 mhz 7 5.5v 4.5 2.8 ma halt mode v in = 0v,v cc @ 2 mhz 7 3.0v 4.0 1.0 ma halt mode v in = 0v,v cc @ 4 mhz 7 5.5v 5.0 3.0 ma halt mode v in = 0v,v cc @ 4 mhz 7 i cc2 standby current 3.0v 10.0 1.0 m a stop mode v in = 0v, v cc wdt is not running 7,8 5.5v 10.0 1.0 m a stop mode v in = 0v,v cc wdt is not running 7,8 i all auto latch low current 3.0v 12.0 3.0 m a 0v < v in < v cc 5.5v 32 16 m a m 0v < v in < v cc i alh auto latch high current 3.0v ?.0 ?.5 m a m 0v < v in < v cc 5.5v ?6.0 ?.0 m a 0v < v in < v cc notes: 1. port 2 and port 0 only 2. v ss = 0v = gnd 3. the device operates down to v lv of the specified frequency for v lv . the minimum operational v cc is determined on the value of the voltage v lv at the ambient temperature. the v lv increases as the temperature decreases. 4. the v cc voltage specification of 3.0 v guarantees 3.3 v 0.3 v with typical values measured at v cc = 3.3v. the v cc voltage specification of 5.5 v guarantees 5.0 v 0.5 v with typical values measured at v cc = 5.0 v. 5. standard mode (not low emi mode) 6. z86e08 only 7. all outputs unloaded and all inputs are at v cc or v ss level. 8. if analog comparator is selected, then the comparator inputs must be at v cc level.
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 11 1 t a = -40 c to +105 c typical note 4 sym parameter v cc [4] min max @ 25 c units conditions notes v inmax max input voltage 4.5v 12.0 v i in < 250 m a1 5.5v 12.0 v i in < 250 m a1 v ch clock input high voltage 4.5v 0.8 v cc v cc +0.3 2.8 v driven by external clock generator 5.5v 0.8 v cc v cc +0.3 2.8 v driven by external clock generator v cl clock input low voltage 4.5v v ss ?.3 0.2 v cc 1.7 v driven by external clock generator 5.5v v ss ?.3 0.2 v cc 1.7 v driven by external clock generator v ih input high voltage 4.5v 0.7 v cc v cc +0.3 2.8 v 5.5v 0.7 v cc v cc +0.3 2.8 v v il input low voltage 4.5v v ss ?.3 0.2 v cc 1.5 v 5.5v v ss ?.3 0.2 v cc 1.5 v v oh output high voltage 4.5v v cc ?.4 4.8 v i oh = ?.0 ma 5 5.5v v cc ?.4 4.8 v i oh = ?.0 ma 5 4.5v v cc ?.4 v low noise @ i oh = ?.5 ma 5.5v v cc ?.4 v low noise @ i oh = ?.5 ma v ol1 output low voltage 4.5v 0.4 0.1 v i ol = +4.0 ma 5 5.5v 0.4 0.1 v i ol = +4.0 ma 5 4.5v 0.4 0.1 v low noise @ i ol = 1.0 ma 5.5v 0.4 0.1 v low noise @ i ol = 1.0 ma v ol2 output low voltage 4.5v 1.0 0.3 v i ol = +12 ma, 5 5.5v 1.0 0.3 v i ol = +12 ma, 5 v offset comparator input offset voltage 4.5v 25.0 10.0 mv 5.5v 25.0 10.0 mv v lv v cc low voltage auto reset 1.8 3.8 2.8 v @ 6 mhz max. int. clk freq. 3 i il input leakage (input bias current of comparator) 4.5v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc i ol output leakage 4.5v ?.0 1.0 m av in = 0v, v cc 5.5v ?.0 1.0 m av in = 0v, v cc v icr comparator input common mode voltage range 0 v cc ?.5 v
z86e04/e08 cmos z8 otp microcontrollers zilog 12 p r e l i m i n a r y ds97z8x0401 dc electrical characteristics (continued) i cc supply current 4.5v 11.0 6.8 ma all output and i/o pins floating @ 2 mhz 5,7 5.5v 11.0 6.8 ma all output and i/o pins floating @ 2 mhz 5,7 4.5v 15.0 8.2 ma all output and i/o pins floating @ 8 mhz 5,7 5.5v 15.0 8.2 ma all output and i/o pins floating @ 8 mhz 5,7 4.5v 20.0 12.0 ma all output and i/o pins floating @ 12 mhz 5,7 5.5v 20.0 12.0 ma all output and i/o pins floating @ 12 mhz 5,7 i cc1 standby current 4.5v 5.0 2.5 ma halt mode v in = 0v, v cc @ 2 mhz 5,7 5.5v 5.0 2.5 ma halt mode v in = 0v, v cc @ 2 mhz 5,7 4.5v 5.0 3.0 ma halt mode v in = 0v, v cc @ 8 mhz 5,7 5.5v 5.0 3.0 ma halt mode v in = 0v, v cc @ 8 mhz 5,7 4.5v 7.0 4.0 ma halt mode v in = 0v, v cc @ 12 mhz 5,7 5.5v 7.0 4.0 ma halt mode v in = 0v, v cc @ 12 mhz 5,7 i cc supply current (low noise mode) 4.5v 11.0 6.8 ma all output and i/o pins floating @ 1 mhz 7 5.5v 11.0 6.8 ma all output and i/o pins floating @ 1 mhz 7 4.5v 13.0 7.5 ma all output and i/o pins floating @ 2 mhz 7 5.5v 13.0 7.5 ma all output and i/o pins floating @ 2 mhz 7 4.5v 15.0 8.2 ma all output and i/o pins floating @ 4 mhz 7 5.5v 15.0 8.2 ma all output and i/o pins floating @ 4 mhz 7 t a = -40 c to +105 c typical note 4 sym parameter v cc [4] min max @ 25 c units conditions notes
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 13 1 t a = -40 c to +105 c typical note 4 sym parameter v cc [4] min max @ 25 c units conditions notes i cc1 standby current (low noise mode) 4.5v 4.0 2.5 ma halt mode v in = 0v, v cc @ 1 mhz 7 5.5v 4.0 2.5 ma halt mode v in = 0v, v cc @ 1 mhz 7 4.5v 4.5 2.8 ma halt mode v in = 0v, v cc @ 2 mhz 7 5.5v 4.5 2.8 ma halt mode v in = 0v, v cc @ 2 mhz 7 4.5v 5.0 3.0 ma halt mode v in = 0v, v cc @ 4 mhz 7 5.5v 5.0 3.0 ma halt mode v in = 0v, v cc @ 4 mhz 7 i cc2 standby current 4.5v 20 1.0 m a stop mode v in = 0v, v cc wdt is not running 7,8 5.5v 20 1.0 m a stop mode v in = 0v, v cc wdt is not running 7,8 i all auto latch low current 4.5v 40 16 m a 0v < v in < v cc 5.5v 40 16 m a 0v < v in < v cc i alh auto latch high current 4.5v ?0.0 ?.0 m a 0v < v in < v cc 5.5v ?0.0 ?.0 m a 0v < v in < v cc notes: 1. port 2 and port 0 only 2. v ss = 0v = gnd 3. the device operates down to v lv of the specified frequency for v lv . the minimum operational v cc is determined on the value of the voltage v lv at the ambient temperature. the v lv increases as the temperature decreases. 4. v cc = 4.5v to 5.5v, typical values measured at v cc = 5.0v 5. standard mode (not low emi mode) 6. z86e08 only 7. all outputs unloaded and all inputs are at v cc or v ss level. 8. if analog comparator is selected, then the comparator inputs must be at v cc level.
z86e04/e08 cmos z8 otp microcontrollers zilog 14 p r e l i m i n a r y ds97z8x0401 ac electrical characteristics figure 6. ac electrical timing diagram 1 3 4 8 2 2 3 t irq in n 6 5 7 7 9 clock
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 15 1 ac electrical characteristics timing table (standard mode for sclk/tclk = xtal/2) t a = 0 c to +70 c 8 mhz 12 mhz no symbol parameter v cc min max min max units notes 1 tpc input clock period 3.0v 125 dc 83 dc ns 1 5.5v 125 dc 83 dc ns 1 2 trc,tfc clock input rise and fall times 3.0v 25 15 ns 1 5.5v 25 15 ns 1 3 twc input clock width 3.0v 62 41 ns 1 5.5v 62 41 ns 1 4 twtinl timer input low width 3.0v 100 100 ns 1 5.5v 70 70 ns 1 5 twtinh timer input high width 3.0v 5tpc 5tpc 1 5.5v 5tpc 5tpc 1 6 tptin timer input period 3.0v 8tpc 8tpc 1 5.5v 8tpc 8tpc 1 7 trtin, tttin timer input rise and fall time 3.0v 100 100 ns 1 5.5v 100 100 ns 1 8 twil int. request input low time 3.0v 100 100 ns 1,2 5.5v 70 70 ns 1,2 9 twih int. request input high time 3.0v 5tpc 5tpc 1 5.5v 5tpc 5tpc 1,2 10 twdt watch-dog timer delay time for timeout 3.0v 25 25 ms 1 5.5v 12 12 ms 1 11 tpor power-on reset time 3.0v 50 180 50 180 ms 1 5.5v 20 80 20 80 ms 1 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31) 3. the v dd voltage specification of 3.0v guarantees 3.3v 0.3v. the v dd voltage specification of 5.5v guarantees 5.0v 0.5v.
z86e04/e08 cmos z8 otp microcontrollers zilog 16 p r e l i m i n a r y ds97z8x0401 ac electrical characteristics timing table (standard mode for sclk/tclk = xtal/2) t a = ?0 c to +105 c 8 mhz 12 mhz no symbol parameter v cc min max min max units notes 1 tpc input clock period 4.5v 125 dc 83 dc ns 1 5.5v 125 dc 83 dc ns 1 2 trc,tfc clock input rise and fall times 4.5v 25 15 ns 1 5.5v 25 15 ns 1 3 twc input clock width 4.5v 62 41 ns 1 5.5v 62 41 ns 1 4 twtinl timer input low width 4.5v 70 70 ns 1 5.5v 70 70 ns 1 5 twtinh timer input high width 4.5v 5tpc 5tpc 1 5.5v 5tpc 5tpc 1 6 tptin timer input period 4.5v 8tpc 8tpc 1 5.5v 8tpc 8tpc 1 7 trtin, tttin timer input rise and fall time 4.5v 100 100 ns 1 5.5v 100 100 ns 1 8 twil int. request input low time 4.5v 70 70 ns 1,2 5.5v 70 70 ns 1,2 9 twih int. request input high time 4.5v 5tpc 5tpc 1 5.5v 5tpc 5tpc 1,2 10 twdt watch-dog timer delay time for timeout 4.5v 10 10 ms 1 5.5v 10 10 ms 1 11 tpor power-on reset time 4.5v 12 100 12 100 ms 1 5.5v 12 100 12 100 ms 1 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request made through port 3 (p33-p31).
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 17 1 ac electrical characteristics low noise mode t a = 0 c to +70 c 1 mhz 4 mhz no symbol parameter v cc min max min max units notes 1 tpc input clock period 3.0v 1000 dc 250 dc ns 1 5.5v 1000 dc 250 dc ns 1 2trc tfc clock input rise and fall times 3.0v 25 25 ns 1 5.5v 25 25 ns 1 3 twc input clock width 3.0v 500 125 ns 1 5.5v 500 125 ns 1 4. twtinl timer input low width 3.0v 100 100 ns 1 5.5v 70 70 ns 1 5 twtinh timer input high width 3.0v 2.5tpc 2.5tpc 1 5.5v 2.5tpc 2.5tpc 1 6 tptin timer input period 3.0v 4tpc 4tpc 1 5.5v 4tpc 4tpc 1 7 trtin, tttin timer input rise and fall time 3.0v 100 100 ns 1 5.5v 100 100 ns 1 8 twil low time int. request input 3.0v 100 100 ns 1,2 5.5v 70 70 ns 1,2 9 twih high time int. request input 3.0v 2.5tpc 2.5tpc 1 5.5v 2.5tpc 2.5tpc 1,2 10 twdt watch-dog timer delay time for timeout 3.0v 25 25 ms 1 5.5v 12 12 ms 1 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31). 3. the v dd voltage specification of 3.0v guarantees 3.3v 0.3v. the v dd voltage specification of 5.5v guarantees 5.0v 0.5v.
z86e04/e08 cmos z8 otp microcontrollers zilog 18 p r e l i m i n a r y ds97z8x0401 ac electrical characteristics (continued) low noise mode t a = ?0 c to +105 c 1 mhz 4 mhz no symbol parameter v cc min max min max units notes 1 tpc input clock period 4.5v 1000 dc 250 dc ns 1 5.5v 1000 dc 250 dc ns 1 2trc tfc clock input rise and fall times 4.5v 25 25 ns 1 5.5v 25 25 ns 1 3 twc input clock width 4.5v 500 125 ns 1 5.5v 500 125 ns 1 4. twtinl timer input low width 4.5v 70 70 ns 1 5.5v 70 70 ns 1 5 twtinh timer input high width 4.5v 2.5tpc 2.5tpc 1 5.5v 2.5tpc 2.5tpc 1 6 tptin timer input period 4.5v 4tpc 4tpc 1 5.5v 4tpc 4tpc 1 7 trtin, tttin timer input rise and fall time 4.5v 100 100 ns 1 5.5v 100 100 ns 1 8 twil int. request input low time 4.5v 70 70 ns 1,2 5.5v 70 70 ns 1,2 9 twih int. request input high time 4.5v 2.5tpc 2.5tpc 1 5.5v 2.5tpc 2.5tpc 1,2 10 twdt watch-dog timer delay time for timeout 4.5v 10 10 ms 1 5.5v 10 10 ms 1 notes: 1. timing reference uses 0.7 v cc for a logic 1 and 0.2 v cc for a logic 0. 2. interrupt request through port 3 (p33-p31).
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 19 1 low noise version low emi emission the z86e04/e08 can be programmed to operate in a low emi emission mode by means of a mask rom bit option. use of this feature results in: n all pre-driver slew rates reduced to 10 ns typical. n internal sclk/tclk operation limited to a maximum of 4 mhz - 250 ns cycle time. n output drivers have resistances of 500 ohms (typical). n oscillator divide-by-two circuitry eliminated. the low emi mode is mask-programmable to be selected by the customer at the time the rom code is submitted. pin functions otp programming mode d7-d0 data bus. data can be read from, or written to, the eprom through this data bus. v cc power supply. it is typically 5v during eprom read mode and 6.4v during the other modes (program, pro- gram verify, and so on). /ce chip enable (active low). this pin is active during eprom read mode, program mode, and program verify mode. /oe output enable (active low). this pin drives the data bus direction. when this pin is low, the data bus is output. when high, the data bus is input. epm eprom program mode. this pin controls the differ- ent eprom program modes by applying different voltages. v pp program voltage. this pin supplies the program volt- age. clear clear (active high). this pin resets the internal ad- dress counter at the high level. clock address clock. this pin is a clock input. the internal address counter increases by one with one clock cycle. /pgm program mode (active low). a low level at this pin programs the data to the eprom through the data bus. application precaution the production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above v cc occur on the xtal1 pin. in addition, processor operation of z8 otp devices may be affected by excessive noise surges on the v pp , /ce, /epm, /oe pins while the microcontroller is in standard mode. recommendations for dampening voltage surges in both test and otp mode include the following: n using a clamping diode to v cc . n adding a capacitor to the affected pin. note: programming the eprom/test mode disable option will prevent accidental entry into eprom mode or test mode.
z86e04/e08 cmos z8 otp microcontrollers zilog 20 p r e l i m i n a r y ds97z8x0401 pin functions (continued) xtal1, xtal2 crystal in, crystal out (time-based input and output, respectively). these pins connect a parallel- resonant crystal, lc, or an external single-phase clock (8 mhz or 12 mhz max) to the on-chip clock oscillator and buffer. port 0, p02-p00. port 0 is a 3-bit bidirectional, schmitt-trig- gered cmos-compatible i/o port. these three i/o lines can be globally configured under software control to be in- puts or outputs (figure 7). auto latch. the auto latch puts valid cmos levels on all cmos inputs (except p33, p32, p31) that are not external- ly driven. a valid cmos level, rather than a floating node, reduces excessive supply current flow in the input buffer. on power-up and reset, the auto latch will set the ports to an undetermined state of 0 or 1. default condition is auto latches enabled. figure 7. port 0 con?uration open out in 1.5 2.3 hysteresis pa d port 0 (i/o) z86e04 and z86e08 auto latch option r 500 k w vcc @ 5.0v
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 21 1 port 2, p27-p20. port 2 is an 8-bit, bit programmable, bi- directional, schmitt-triggered cmos-compatible i/o port. these eight i/o lines can be configured under software control to be inputs or outputs, independently. bits pro- grammed as outputs can be globally programmed as ei- ther push-pull or open-drain (figure 8). figure 8. port 2 con?uration open-drain open out in 1.5 2.3 hysteresis pad port 2 (i/o) port 2 z86e04 and z86e08 auto latch option r 500 k w vcc @ 5.0v
z86e04/e08 cmos z8 otp microcontrollers zilog 22 p r e l i m i n a r y ds97z8x0401 pin functions (continued) port 3, p33-p31 . port 3 is a 3-bit, cmos-compatible port with three fixed input (p33-p31) lines. these three input lines can be configured under software control as digital schmitt-trigger inputs or analog inputs. these three input lines are also used as the interrupt sources irq0-irq3, and as the timer input signal t in (fig- ure 9). figure 9. port 3 con?uration port 3 z86e04 and z86e08 d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) cc dig. an. + - + - v tin p31 data latch irq2 irq3 p32 data latch irq0 p33 data latch irq1 pa d pa d pa d 0 = digital 1 = analog irq 0,1,2 = falling edge detection irq3 = rising edge detection
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 23 1 comparator inputs. two analog comparators are added to input of port 3, p31, and p32, for interface flexibility. the comparators reference voltage p33 (ref) is common to both comparators. typical applications for the on-board comparators; zero crossing detection, a/d conversion, voltage scaling, and threshold detection. in analog mode, p33 input functions serve as a reference voltage to the comparators. the dual comparator (common inverting terminal) features a single power supply which discontinues power in stop mode. the common voltage range is 0-4 v when the v cc is 5.0v; the power supply and common mode rejection ra- tios are 90 db and 60 db, respectively. interrupts are generated on either edge of comparator 2's output, or on the falling edge of comparator 1's output. the comparator output is used for interrupt generation, port 3 data inputs, or t in through p31. alternatively, the comparators can be disabled, freeing the reference input (p33) for use as irq1 and/or p33 input. functional description the following special functions have been incorporated into the z86e04/e08 devices to enhance the standard z8 core architecture to provide the user with increased design flexibility. reset . this function is accomplished by means of a pow- er-on reset or a watch-dog timer reset. upon power- up, the power-on reset circuit waits for t por ms, plus 18 clock cycles, then starts program execution at address 000c (hex) (figure 10). the z86e04/e08 control registers' reset value is shown in table 3. power-on reset (por) . a timer circuit clocked by a ded- icated on-board rc oscillator is used for a por timer func- tion. the por time allows v cc and the oscillator circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of the four following conditions: n power-bad to power-good status n stop-mode recovery n wdt time-out n wdh time-out watch-dog timer reset. the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is initially enabled by executing the wdt instruction and is retriggered on subsequent execution of the wdt instruction. the timer circuit is driven by an on- board rc oscillator. figure 10. internal reset con?uration int osc xtal osc por (cold start) p27 (stop mode) 18 clk reset filiter chip reset delay line tpor msec
z86e04/e08 cmos z8 otp microcontrollers zilog 24 p r e l i m i n a r y ds97z8x0401 functional description (continued) table 3. z86e04/e08 control registers reset condition addr. reg. d7 d6 d5 d4 d3 d2 d1 d0 comments ff spl 0 0 0 0 0 0 0 0 fd rp 0 0 0 0 0 0 0 0 fc flags u u u u u u u u fb imr 0 u u u u u u u fa irq u u 0 0 0 0 0 0 irq3 is used for positive edge detection f9 ipr u u u u u u u u f8* p01m u u u 0 u u 0 1 f7* p3m u u u u u u 0 0 f6* p2m 1 1 1 1 1 1 1 1 inputs after reset f5 pre0 u u u u u u u 0 f4 t0 u u u u u u u u f3 pre1 u u u u u u 0 0 f2 t1 u u u u u u u u f1 tmr 0 0 0 0 0 0 0 0 note: *registers are not reset after a stop-mode recovery using p27 pin. a subsequent reset will cause these control registers to be reconfigured as shown in table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 25 1 program memory. the z86e04/e08 addresses up to 1k/2kb of internal program memory (figure 11). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors that cor- respond to the six available interrupts. bytes 0-1024/2048 are on-chip one-time programmable rom. register file . the register file consists of three i/o port registers, 124 general-purpose registers, and 14 control and status registers r0-r3, r4-r127 and r241-r255, re- spectively (figure 12). general-purpose registers occupy the 04h to 7fh address space. i/o ports are mapped as per the existing cmos z8. figure 11. program memory map 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 1023/2047 0ch 0bh 0ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h 3fh/7ffh figure 12. register file spl stack pointer (bits 7-0) general-purpose register register pointer program control flags interrupt mask register interrupt request register interrupt priority register ports 0-1 mode port 3 mode port 2 mode t0 prescaler timer/counter 0 t1 prescaler timer/counter 1 timer mode not implemented general-purpose registers port 3 port 2 reserved port 0 rp imr irq ipr p3m p2m pre0 t0 pre1 t1 tmr p3 p2 p1 p0 p01m flags indentifiers location 255 (ffh) 254 (fe) 253 (fd) 252 (fc) 251 (fb) 250 (fa) 249 (f9) 248 (f8) 247 (f7) 246 (f6) 245 (f5) 244 (f4) 243 (f3) 242 (f2) 241 (f1h) 4 3 2 1 0 (00h) 128 127 (7fh) gpr
z86e04/e08 cmos z8 otp microcontrollers zilog 26 p r e l i m i n a r y ds97z8x0401 functional description (continued) the z86e04/e08 instructions can access registers directly or indirectly through an 8-bit address field. this allows short 4-bit register addressing using the register pointer. in the 4-bit mode, the register file is divided into eight work- ing register groups, each occupying 16 continuous loca- tions. the register pointer (figure 13) addresses the starting location of the active working-register group. stack pointer. the z86e04/e08 has an 8-bit stack point- er (r255) used for the internal stack that resides within the 124 general-purpose registers. general-purpose registers (gpr). these registers are undefined after the device is powered up. the registers keep their last value after any reset, as long as the reset occurs in the v cc voltage-specified operating range. note: register r254 has been designated as a general-purpose register and is set to 00 hex after any reset or stop-mode recovery. counter/timer. there are two 8-bit programmable counter/timers (t0 and t1), each driven by its own 6-bit programmable prescaler. the t1 prescaler is driven by in- ternal or external clock sources; however, the t0 can be driven by the internal clock source only (figure 15). the 6-bit prescalers divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. when both counter and prescaler reach the end of count, a timer interrupt re- quest irq4 (t0) or irq5 (t1) is generated. the counter can be programmed to start, stop, restart to continue, or restart from the initial value. the counters are also programmed to stop upon reaching zero (single-pass mode) or to automatically reload the initial value and con- tinue counting (modulo-n continuous mode). the counters, but not the prescalers, are read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and is either the internal mi- croprocessor clock divided by four, or an external signal in- put through port 3. the timer mode register configures the external timer input (p31) as an external clock, a trigger in- put that is retriggerable or non-retriggerable, or used as a gate input for the internal clock. figure 13. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group. r7 r6 r5 r4 r253 (register pointer) i/o ports specified working register group the lower nibble of the register file address provided by the instruction points to the specified register. r3 r2 r1 r0 register group 1 register group 0 r15 to r0 register group f r15 to r4* r3 to r0 r15 to r0 ff f0 0f 00 1f 10 2f 20 3f 30 4f 40 5f 50 6f 60 7f 70 *expanded register group (0) is selected in this figure by handling bits d3 to d0 as "0" in register r253(rp).
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 27 1 * note : by passed, if low emi mode is selected. figure 14. counter/timers block diagram osc pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ? 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register ? 2 clock logic irq4 irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock ? 4
z86e04/e08 cmos z8 otp microcontrollers zilog 28 p r e l i m i n a r y ds97z8x0401 functional description (continued) interrupts. the z86e04/e08 has six interrupts from six different sources. these interrupts are maskable and pri- oritized (figure 15). the sources are divided as follows: the falling edge of p31 (an1), p32 (an2), p33 (ref), the rising edge of p32 (an2), and two counter/timers. the in- terrupt mask register globally or individually enables or disables the six interrupt requests (table 4). when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the interrupt priority register. all z86e04/e08 in- terrupts are vectored through locations in program memory. when an interrupt machine cycle is activated, an interrupt request is granted. this disables all subsequent interrupts, saves the program counter and status flags, and then branches to the program memory vector location reserved for that interrupt. this memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service. note: user must select any z86e08 mode in zilog's c12 icebox emulator. the rising edge interrupt is not sup- ported on the z86ccp00zem emulator. table 4. interrupt types, sources, and vectors vector name source location comments irq0 an2(p32) 0,1 external (f)edge irq1 ref(p33) 2,3 external (f)edge irq2 an1(p31) 4,5 external (f)edge irq3 an2(p32) 6,7 external (r)edge irq4 t0 8,9 internal irq5 t1 10,11 internal notes: f = falling edge triggered r = rising edge triggered figure 15. interrupt block diagram irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 - irq5
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 29 1 clock. the z86e04/e08 on-chip oscillator has a high- gain, parallel-resonant amplifier for connection to a crystal, lc, rc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, up to 12 mhz max., with a series resis- tance (rs) of less than or equal to 100 ohms. the crystal should be connected across xtal1 and xtal2 using the vendors crystal recommended capacitors from each pin directly to device ground pin 14 (figure 16). note that the crystal capacitor loads should be connected to v ss , pin 14 to reduce ground noise injection. figure 16. oscillator con?uration xtal1 xtal2 c1 c2 c1 c2 c1 xtal1 xtal2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 47 pf typ * f = 8 mhz lc rc @ 5v vcc (typ) c1 = 100 pf r = 2k f = 6 mhz external clock l r * typical value including pin parasitics * * * * *
z86e04/e08 cmos z8 otp microcontrollers zilog 30 p r e l i m i n a r y ds97z8x0401 functional description (continued) table 5. typical frequency vs. rc values v cc = 5.0v @ 25 c load capacitor resistor (r) 33 pfd 56 pfd 100 pfd 0.00 1 m fd a(hz) b(hz) a(hz) b(hz) a(hz) b(hz) a(hz) b(hz) 1.0m 33k 31k 20k 20k 12k 11k 1.4k 1.4k 560k 56k 52k 34k 32k 20k 19k 2.5k 2.4k 220k 144k 130k 84k 78k 48k 45k 6k 6k 100k 315k 270k 182k 164k 100k 95k 12k 12k 56k 552k 480k 330k 300k 185k 170k 23k 22k 20k 1.4m 1m 884k 740k 500k 450k 65k 61k 10k 2.6m 2m 1.6m 1.3m 980k 820k 130k 123k 5k 4.4m 3m 2.8m 2m 1.7k 1.3m 245k 225k 2k 8m 5m 6m 4m 3.8k 2.7m 600k 536k 1k 12m 7m 8.8m 6m 6.3k 4.2m 1.0m 950k notes: a = std mode frequency. b = low emi mode frequency. table 6. typical frequency vs. rc values v cc = 5.0v @ 25 c load capacitor resistor (r) 33 pfd 56 pfd 100 pfd 0.00 1 m fd a(hz) b(hz) a(hz) b(hz) a(hz) b(hz) a(hz) b(hz) 1.0m 18k 18k 12k 12k 7.4k 7.7k 1k 1k 560k 30k 30k 20k 20k 12k 12k 1.6k 1.6k 220k 70k 70k 47k 47k 30k 30k 4k 4k 100k 150k 148k 97k 96k 60k 60k 8k 8k 56k 268k 250k 176k 170k 100k 100k 15k 15k 20k 690m 600k 463k 416k 286k 266k 40k 40k 10k 1.2m 1m 860k 730k 540k 480k 80k 76k 5k 2m 1.7m 1.5m 1.2m 950k 820k 151k 138k 2k 4.6m 3m 3.3m 2.4m 2.2m 1.6m 360k 316k 1k 7m 4.6m 5m 3.6m 3.6k 2.6m 660k 565k notes: a = std mode frequency. b = low emi mode frequency.
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 31 1 halt mode. this instruction turns off the internal cpu clock but not the crystal oscillation. the counter/timers and external interrupts irq0, irq1, irq2 and irq3 remain ac- tive. the device is recovered by interrupts, either external- ly or internally generated. an interrupt request must be ex- ecuted (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after the halt. note: on the c12 icebox, the irq3 does not wake the device out of halt mode. stop mode. this instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 m a. the stop mode is released by a reset through a stop-mode recovery (pin p27). a low input condition on p27 releases the stop mode. program exe- cution begins at location 000c(hex). however, when p27 is used to release the stop mode, the i/o port mode reg- isters are not reconfigured to their default power-on condi- tions. this prevents any i/o, configured as output when the stop instruction was executed, from glitching to an un- known state. to use the p27 release approach with stop mode, use the following instruction: note: a low level detected on p27 pin will take the device out of stop mode even if configured as an output. in order to enter stop or halt mode, it is necessary to first flush the instruction pipeline to avoid suspending exe- cution in mid-instruction. to do this, the user executes a nop (opcode=ffh) immediately before the appropriate sleep instruction, such as: watch-dog timer (wdt). the watch-dog timer is en- abled by instruction wdt. when the wdt is enabled, it cannot be stopped by the instruction. with the wdt in- struction, the wdt is refreshed when it is enabled within every 1 twdt period; otherwise, the controller resets itself, the wdt instruction affects the flags accordingly; z=1, s=0, v=0. wdt = 5f (hex) opcode wdt (5fh). the first time opcode 5fh is execut- ed, the wdt is enabled and subsequent execution clears the wdt counter. this must be done at least every t wdt ; otherwise, the wdt times out and generates a reset. the generated reset is the same as a power-on reset of t por , plus 18 xtal clock cycles. the software enabled wdt does not run in stop mode. opcode wdh (4fh). when this instruction is executed it enables the wdt during halt. if not, the wdt stops when entering halt. this instruction does not clear the counters, it just makes it possible to have the wdt running during halt mode. a wdh instruction executed without executing wdt (5fh) has no effect. permanent wdt. selecting the hardware enabled perma- nent wdt option, will automatically enable the wdt upon exiting reset. the permanent wdt will always run in halt mode and stop mode, and it cannot be disabled. auto reset voltage (v lv ). the z86e04/e08 has an auto- reset built-in. the auto-reset circuit resets the z86e04/e08 when it detects the v cc below v lv . figure 18 shows the auto reset voltage versus tempera- ture. if the v cc drops below the vcc operating voltage range, the z86e04/e08 will function down to the v lv un- less the internal clock frequency is higher than the speci- fied maximum v lv frequency. ld p2m, #1xxx xxxxb nop stop x = dependent on user's application. ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode
z86e04/e08 cmos z8 otp microcontrollers zilog 32 p r e l i m i n a r y ds97z8x0401 functional description (continued) figure 17. typical auto reset voltage (v lv ) vs. temperature 2.4 2.5 2.6 2.7 2.8 2.9 vcc (volts) C40 c 40 c temp 2.3 C20 c0 c20 c 60 c80 c 100 c
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 33 1 low emi emission the z86e04/e08 can be programmed to operate in a low emi emission (low noise) mode by means of an eprom programmable bit option. use of this feature results in: n less than 1 ma consumed during halt mode. n all drivers slew rates reduced to 10 ns (typical). n internal sclk/tclk = xtal operation limited to a maximum of 4 mhz - 250 ns cycle time. n output drivers have resistances of 500 ohms (typical). n oscillator divide-by-two circuitry eliminated. the z86e04/e08 offers programmable rom protect and programmable low noise features. when programmed for low noise, the rom protect feature is optional. in addition to v dd and gnd (v ss ), the z86e04/e08 chang- es all its pin functions in the eprom mode. xtal2 has no function, xtal1 functions as /ce, p31 functions as /oe, p32 functions as epm, p33 functions as v pp , and p02 functions as /pgm. rom protect. rom protect fully protects the z86e04/e08 rom code from being read externally. when rom protect is selected, the instructions ldc and ldci are supported (z86e04/e08 and z86c04/c08 do not support the instruc- tions of lde and ldei). when the device is programmed for rom protect, the low noise feature will not automati- cally be enabled. please note that when using the device in a noisy environ- ment, it is suggested that the voltages on the epm and ce pins be clamped to v cc through a diode to v cc to prevent accidentally entering the otp mode. the v pp requires both a diode and a 100 pf capacitor. auto latch disable. auto latch disable option bit when programmed will globally disable all auto latches. wdt enable. the wdt enable option bit, when pro- grammed, will have the hardware enabled permanent wdt enabled after exiting reset and can not be stopped in halt or stop mode. eprom/test mode disable. the eprom/test mode disable option bit, when programmed, will disable the eprom mode and the factory test mode. reading, veri- fying, and programming the z8 will be disabled. to fully verify that this mode is disabled, the device must be power cycled. user modes. table 7 shows the programming voltage of each mode of z86e04/e08. table 7. otp programming table programming modes v pp epm /ce /oe /pgm addr data v cc * eprom read1 nu v h v il v il v ih addr out 4.5v? eprom read2 nu v h v il v il v ih addr out 5.5v? program v h xv il v ih v il addr in 6.4v program verify v h xv il v il v ih addr out 6.4v eprom protect v h v h v h v ih v il nu nu 6.4v low noise select v h v ih v h v ih v il nu nu 6.4v auto latch disable v h v ih v h v il v il nu nu 6.4v wdt enable v h v il v h v ih v il nu nu 6.4v eprom/test mode v h v il v h v il v il nu nu 6.4v notes: 1. v h =13.0v 0.25 v dc . 2. v ih = as per specific z8 dc specification. 3. v il = as per specific z8 dc specification. 4. x = not used, but must be set to v h or v ih level. 5. nu = not used, but must be set to either v ih or v il level. 6. i pp during programming = 40 ma maximum. 7. i cc during programming, verify, or read = 40 ma maximum. 8. * v cc has a tolerance of - 0.25v. 9. ? v cc = 5.0v is acceptable.
z86e04/e08 cmos z8 otp microcontrollers zilog 34 p r e l i m i n a r y ds97z8x0401 functional description (continued) internal address counter. the address of z86e04/e08 is generated internally with a counter clocked through pin p01 (clock). each clock signal increases the address by one and the ?igh?level of pin p00 (clear) will reset the ad- dress to zero. figure 18 shows the setup time of the serial address input. programming waveform. figures 19, 20 and 21 show the programming waveforms of each mode. table 8 shows the timing of programming waveforms. programming algorithm. figure 22 shows the flow chart of the z86e04/e08 programming algorithm. table 8. timing of programming waveforms parameters name min max units 1 address setup time 2 m s 2 data setup time 2 m s 3v pp setup 2 m s 4v cc setup time 2 m s 5 chip enable setup time 2 m s 6 program pulse width 0.95 ms 7 data hold time 2 m s 8 /oe setup time 2 m s 9 data access time 188 ns 10 data output float time 100 ns 11 overprogram pulse width 2.85 ms 12 epm setup time 2 m s 13 /pgm setup time 2 m s 14 address to /oe setup time 2 m s 15 option program pulse width 78 ms 16 /oe width 250 ns 17 address valid to /oe low 125 ns
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 35 1 figure 18. z86e04/e08 address counter waveform p01 = clock p00 = clear t2 t4 t3 t1 internal address t5 0 min 9 data vih vil invalid valid invalid valid legend: t1 reset clock width t2 input clock high t3 input clock period t4 input clock low t5 clock to address counter out delay t6 epm/vpp set up time 30 ns min 100 ns min 200 ns min 100 ns min 15 ns max 40 m s min t6 vpp/epm
z86e04/e08 cmos z8 otp microcontrollers zilog 36 p r e l i m i n a r y ds97z8x0401 functional description (continued) figure 19. z86e04/e08 programming waveform (eprom read) data vih vil invalid valid invalid valid vih vil address stable address address stable 17 9 12 5 epm vh vil vcc 4.5v /ce vih vil /oe vih vil vpp vh vil 5.5v /pgm vih vil 3 16 16 17 16
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 37 1 figure 20. z86e04/e08 programming waveform (program and verify) address v ih v il address stable data v ih v il data stable data out valid 1 2 10 9 3 v pp v h v ih epm v il 4 7 /ce v il 6 8 11 /pgm v ih v il v ih v h vcc 4.5v 6v /oe v ih v il program cycle verify cycle 16 13 5
z86e04/e08 cmos z8 otp microcontrollers zilog 38 p r e l i m i n a r y ds97z8x0401 functional description (continued) figure 21. z86e04/e08 programming options waveform (eprom protect and low noise program) address v ih v il data v ih v il v pp v ih v cc 6v /oe 3 4 5 /ce v h v ih /pgm v ih v il 12 15 15 epm v h v il eprom protect low noise 4.5v v ih v ih v ih v h 12 13 13
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 39 1 figure 22. z86e04/e08 programming options waveform (auto latch disable, permanent wdt enable and eprom/test mode disable) address v ih v il data v ih v il v pp v ih v cc 6v /oe 3 4 5 /ce v h v ih /pgm v ih v il 12 15 15 epm v ih auto latch wdt 4.5v v il v il v ih v h 12 12 12 15 eprom/test mode disable 13 13 13 13
z86e04/e08 cmos z8 otp microcontrollers zilog 40 p r e l i m i n a r y ds97z8x0401 functional description (continued) figure 23. z86e04/e08 programming algorithm start vcc = 6.4v vpp = 13.0v n = 0 program 1 ms pulse increment n n = 25 ? ye s no verify one byte pass fail prog. one pulse 3xn ms duration verify byte fail pass increment address last addr ? ye s no vcc = vpp = 4.5v verify all bytes device failed addr = first location fail pass vcc = vpp = 5.5v verify all bytes device passed pass fail
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 41 1 z8 control registers figure 24. timer mode register (f1 h : read/write) figure 25. counter timer 1 register (f2 h : read/write) figure 26. prescaler 1 register (f3 h : write only) d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count 1 enable t0 count 0 no function 1 load t0 0 no function 1 load t1 0 disable t1 count 1 enable t1 count tin modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) reserved (must be 0) r241 tmr d7 d6 d5 d4 d3 d2 d1 d0 t initial value (when written) (range 1-256 decimal 01-00 hex) t current value (when read) 1 1 r242 t1 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 = t single pass 1 = t modulo n 1 1 clock source 1 = t internal 0 = t external timing input (t ) mode in 1 1 prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 figure 27. counter/timer 0 register (f4 h : read/write) figure 28. prescaler 0 register (f5 h : write only) figure 29. port 2 mode register (f6 h : write only) figure 30. port 3 mode register (f7 h : write only) d7 d6 d5 d4 d3 d2 d1 d0 t initial value (when written) (range: 1-256 decimal 01-00 hex) t current value (when read) 0 0 r244 t0 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t0 single pass 1 t0 modulo n reserved (must be 0) r245 pre0 prescaler modulo (range: 1-64 decimal 01-00 hex) d7 d6 d5 d4 d3 d2 d1 d0 p2 - p2 i/o definition 0 defines bit as output 1 defines bit as input 70 r246 p2m d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 open-drain 1 port 2 push-pull reserved (must be 0) port 3 inputs 0 digital mode 1 analog mode
z86e04/e08 cmos z8 otp microcontrollers zilog 42 p r e l i m i n a r y ds97z8x0401 z8 control registers (continued) figure 31. port 0 and 1 mode register (f8 h : write only) figure 32. interrupt priority register (f9 h : write only) figure 33. interrupt request register (fa h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 p0 2 -p0 0 mode 00 = output 01 = input reserved (must be 1.) r248 p01m reserved (must be 0.) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority reserved = 000 c > a > b = 001 a > b > c = 010 a > c > b = 01 1 b > c > a = 100 c > b > a = 101 b > a > c = 110 reserved = 111 irq3, irq5 priority (group a) 0 = irq5 > irq3 1 = irq3 > irq5 irq0, irq2 priority (group b) 0 = irq2 > irq0 1 = irq0 > irq2 irq1, irq4 priority (group c) 0 = irq1 > irq4 1 = irq4 > irq1 reserved (must be 0.) r249 ipr d7 d6 d5 d4 d3 d2 d1 d0 r250 irq reserved (must be 0) irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = p32 input irq4 = t0 irq5 = t1 figure 34. interrupt mask register (fb h : read/write) figure 35. flag register (fc h : read/write) figure 36. register pointer (fd h : read/write) figure 37. stack pointer (ff h : read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0.) 1 enables irq0-irq5 (d = irq0) 1 enables interrupts 0 r251 imr d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag r252 flags d7 d6 d5 d4 d3 d2 d1 d0 r253 rp expanded register file working register pointer default after reset = 00h d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp - sp ) 0 7 r255 spl
z86e04/e08 zilog cmos z8 otp microcontrollers ds97z8x0401 p r e l i m i n a r y 43 1 package information 18-pin dip package diagram 18-pin soic package diagram
z86e04/e08 cmos z8 otp microcontrollers zilog 44 p r e l i m i n a r y ds97z8x0401 ordering information z86e04 z86e08 for fast results, contact your local zilog sales office for assistance in ordering the part(s) desired. codes preferred package p = plastic dip longer lead time s = soic preferred temperature s = 0 c to +70 c e = ?0 c to +105 c speeds 12 =12 mhz environmental c = plastic standard ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax (408) 370-8056 internet: www.zilog.com standard and extended temperature 18-pin dip 18-pin soic z86e0412psc z86e04012sc z86e0412pec z86e0412sec standard and extended temperature 18-pin dip 18-pin soic z86e0812psc z86e0812ssc z86e0812pec Z86E0812SEC example: z 86e04 12 p s c environmental flow temperature package speed product number zilog prefix is a z86e04, 12 mhz, dip, 0 c to +70 c, plastic standard flow

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